There are generally three logic families for use in digital systems: transistor-transistor logic (TTL), complementary metal-oxide semiconductor logic (CMOS), and emitter-coupled logic (ECL). The use of a particular logic family within an electrical design is governed mainly by design considerations such as speed, power consumption, noise immunity, cost, availability, and ease of interfacing with other logic families.
TTL has been the most widely used logic family for many years in applications that use small-scale integration and medium-scale integration. The TTL family is powered by a supply voltage of five volts. Correspondingly, there is a proliferation of systems in the electronics industry which utilize five volt power supplies as either the main power supply or at least one of the primary power supplies.
There are many integrated circuits (ICs) within the CMOS logic family that are compatible (i.e., five volt compliant) with TTL. This allows for the introduction of both TTL and CMOS integrated circuits within an electrical design without the need to provide additional circuitry to interface the different logic families together.
In many cases, the digital output signal of a CMOS integrated circuit is made TTL compatible by using a standard CMOS inverter, scaled appropriately to drive an off-chip TTL load, as a pad driver which is bonded to the pin of the CMOS integrated circuit package. The pin of the CMOS integrated circuit is connected to other integrated circuits by means of a system board such as a printed circuit board (PCB).
It is well known that CMOS integrated circuits with gate oxides thicker than approximately 120 Angstroms can safely and reliably operate with a supply voltage of five volts. However, in the semiconductor industry there has emerged a trend toward the development of low voltage, high-density, sub-micron processing technologies. Thus, as CMOS integrated circuit technologies continue to shrink in physical size, the supply voltage that these processes are capable of supporting is also reduced.
For instance, in a sub 0.5mm CMOS process, the gate oxide is often reduced to 90 Angstroms which is not capable of supporting a five volt power supply in a reliable fashion. Long term exposure of such a small geometry gate oxide to a voltage greater than 3.3 volts can lead to failure of the CMOS integrated circuit. Nevertheless, some systems that include smaller geometry silicon integrated circuits are still operated with a supply voltage of five volts.
To reduce the stress on the smaller geometry integrated circuits, digital libraries have been developed which operate with supply voltages of 3.3 volts or less, rather than at the traditional five volt level. However, it has not been possible to convert all the myriads of electronic devices to operate by using less than five volts. For example, a newer sub-micron CMOS microprocessor may operate at 3.3 volts while the only I/O buffers available to use with the microprocessor are 5-volt ICs from the TTL logic family. Thus, some ICs in the circuit design may require a supply voltage of five volts while others must operate at 3.3 volts.
If both 5 volt integrated circuits and 3.3 volt sub-micron integrated circuits are used in an electrical design, then additional measures must be taken to interface the circuits together. These extra steps are needed since smaller geometry integrated circuits are precluded from driving out a true five volt logic signal because of their reduced voltage restriction. Thus, voltage level translators or shifters are required between those sub-micron integrated circuits operating at 3.3 volts and those integrated circuits operating at five volts.
A typical solution to the above-stated voltage level shifting problem is to use special level shifter ICs between the circuits having five volt logic inputs and the 3.3 volt sub-micron CMOS outputs. The level shifter ICs are capable of responding to a low voltage swing (3.3 volts) digital input and driving out a full five volt output signal. However, such level shifters are fabricated using a larger geometry CMOS process (i.e., larger than sub-micron) or some other silicon process capable of supporting both five volt supply voltages and five volt gate oxide voltages.
Another alternative to the level shifting problem is to drive a five volt powered CMOS integrated circuit directly with the output of a 3.3 volt sub-micron integrated circuit and adjust the threshold levels of the five volt powered CMOS device to accept the reduced output voltage swing of the 3.3 volt device. However, in some cases, reducing the input threshold levels of existing integrated circuits can be costly.
The present invention overcomes the above-discussed problems by providing a sub-micron CMOS output driver that can generate a five volt digital output without overstressing the gate oxides of the driver.